This invention relates to a programmable logic device (PLD) or field programmable gate array (FPGA). In particular, it relates to the implementation of an address decoder in such a device.
A programmable logic device is an integrated circuit, which includes a large number of logic elements, usually arranged in the form of an array. After manufacture, these logic elements can be combined, by programming the possible interconnections between the logical elements in a particular way, so that the device performs a particular desired set of functions.
In order to allow the required interconnections to be made, the programmable logic device includes a routing structure. The routing structure allows communication between the different logic elements in the array.
After manufacture of the programmable logic device, functions are allocated to the logic elements, and the interconnections between the logic elements are programmed, in such a way that the device performs its intended overall function.
In many cases, it is useful to use a programmable logic device to implement a device which operates with a bus structure. That is, multiple functional blocks are implemented within the programmable logic device and are interconnected such that any one of a first group of said blocks, referred to as master devices, can initiate data transfer to or from any one of a second group of said blocks, referred to as slave devices.
In order for a bus structure of this type to operate, it is necessary for transferred data to be sent with an appropriate address, and the address must then be decoded to ensure that data is read from, or written to, the intended functional block. One way of implementing this address decoder in a programmable logic device is to use the logic elements. However, this uses the logic elements somewhat inefficiently, while preventing them from being used for other purposes.